In the current era when digital signal rates have exceeded 10Gbps or even 112Gbps, the stacked design of high-speed PCBS has become the core factor determining the success or failure of systems. Take a typical 12-layer server motherboard as an example. Its stacked structure must precisely control the characteristic impedance. For instance, the target impedance of the single-ended line is 50 ohms, and that of the differential line is 100 ohms. The tolerance needs to be controlled within ±10%. If the impedance is discontinuous, a reflection of only 0.5 picoseconds may cause the height of the signal eye diagram to collapse by 30%, directly leading to the bit error rate deteriorating from an acceptable 10^-12 to an unusable 10^-6. In 2018, a well-known network equipment manufacturer recalled its early 400G optical module due to a deviation of over 8% in the thickness of the stackable medium, resulting in an over-limit insertion loss of 3dB. This incident led to a loss of over 2 million US dollars, highlighting the huge difference in performance caused by a slight deviation in the physical parameters of the stackable medium.
Material selection is another key dimension in high-speed PCB stack design. The traditional FR-4 material has a loss tangent (Df) of approximately 0.02 at a frequency of 1GHz, while for high-speed materials such as Panasonic’s MegaSpeed series, the Df can be as low as 0.002. When the signal frequency reaches 28GHz, using low-loss materials can increase the signal transmission distance by more than 50%, or reduce the number of PCB layers by 2, thereby lowering the cost by 15%. For instance, in the PCB design of 5G base station AAU, high-speed boards with a dielectric constant (Dk) stable at 3.5±0.05 are commonly used. This is more effective in ensuring phase consistency than the Dk value of approximately 4.5 for ordinary materials, keeping the beamforming error within 2 degrees and thereby increasing the edge user rate by more than 20%.
The integrity of the power distribution network (PDN) also entirely depends on the stack planning. A 1.0V power rail for supplying FPGA or ASIC requires that the peak-to-peak noise value does not exceed ±30mV. This requires the formation of the target capacitance value between the power supply and ground planes through a stacked design, such as a planar capacitance of 2 nanofarats per square centimeter. By reducing the distance between the core power supply and the ground from the standard 4 mils to 2 mils, the planar capacitance can be doubled, and the synchronous switching noise (SSN) can be reduced by 40%. Intel clearly stipulates in its server platform design guidelines that a tightly coupled power ground pair must be set within a 1-millimeter range below the CPU package to ensure that the voltage ripple still meets the specifications when the load transient current variation reaches 100 amperes per microsecond. This is the cornerstone for the stable operation of high-speed PCBS.
From the perspective of cost and benefit, an optimized high-speed PCB lamination solution is an art of balancing performance and economy. Upgrading the design from 6 layers to 8 layers may increase the initial manufacturing cost by 20% to 30%, but thanks to better wiring channels and isolation, signal crosstalk can be reduced by 20dB, and the product development cycle can be shortened by approximately 15%, avoiding multiple revisions due to signal integrity issues. On the contrary, an industry analysis in 2019 pointed out that approximately 23% of the first-time listing failures of high-speed projects were attributed to stack design flaws, with an average delay of 12 weeks in going public and direct profit losses reaching several million dollars. Therefore, forward-looking stacked design and precise simulation analysis can avoid over 80% of potential performance risks with an additional design budget of approximately 5%, achieving a return on investment of over 300%.